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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. a 05/11/09 is 62wv10248dall/bll is6 5wv10248dall/bll copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. 1m x 8 low voltage, ultra low power cmos static ram features ? high-speed access time: 45ns, 55ns ? cmos low power operation C 30 mw (typical) operating C 12 w (typical) cmos standby ? ttl compatible interface levels ? single power supply C 1.65v--2.2v v d d (62/65wv10248d all) C 2.4v--3.6v v d d (62/65wv10248dbll) ? fully static operation: no clock or refresh required ? three state outputs ? data control for upper and lower bytes ? automotive temperature (-40 o c to +125 o c) ? lead-free available description the issi is62wv10248dall/ is62wv10248dbll are high-speed, 8m bit static rams organized as 1m words by 8 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. the is62wv10248dall and is62wv10248dbll are packaged in the jedec standard 48-pin mini bga (9mm x 11mm) and 44-pin tsop (type ii). functional block diagram may 2009 a0-a19 cs1 oe we 1m x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 cs2
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll pin descriptions a0-a19 address inputs cs1 chip enable 1 input cs2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output nc no connection v d d power gnd ground 48-pin mini bga (b) (9mm x 11mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 nc nc i/o0 i/o1 v dd gnd i/o2 i/o3 nc nc we a19 a18 a17 a16 a15 a5 a6 a7 oe cs2 a8 nc nc i/o7 i/o6 gnd v dd i/o5 i/o4 nc nc a9 a10 a11 a12 a13 a14 44-pin tsop (type ii) pin configuration (1m x 8 low power) 1 2 3 4 5 6 a b c d e f g h nc oe a 0 a 1 a 2 cs 2 nc nc a 3 a 4 cs1 nc i/o 0 a 5 a 6 nc i/o 4 gnd i/o 1 a 17 a 7 i/o 5 v dd v dd i/o 2 nc a 16 i/o 6 v ss i/o 3 nc a 14 a 15 nc i/o 7 nc a 12 a 13 we nc a 18 a 8 a 9 a 10 a 11 a 19 nc nc
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll operating range (v d d ) range ambient temperature 1.65v - 2.2v 2.4v - 3.6v commercial 0c to +70c is62wv10248d all (55ns) is62wv10248dbll (55ns)* industrial C40c to +85c is62wv10248d all (55ns) is62wv10248dbll (55ns)* automotive C40c to +125c is65wv10248d all (70ns) is65wv10248dbll (55ns) *when operated in the range for 3.3v 5% or when operated in the temperature range of 0c to 70c, the device meets 45ns. capacitance (1,2) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 5 pf c o u t output capacitance v o u t = 0v 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v d d = 3.0v. truth table mode we cs1 cs2 oe i/o operation v d d current not selected x h x x high-z i s b 1 , i s b 2 (power-down) x x l x high-z i s b 1 , i s b 2 output disabled h l h h high-z i c c read h l h l d o u t i c c write l l h x d i n i c c
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll dc electrical characteristics (over operating range) symbol parameter test conditions v d d min. max. unit v o h output high voltage i o h = -0.1 ma 1.65-2.2v 1.4 v i o h = -1 ma 2.4-3.6v 1.8 v v o l output low voltage i o l = 0.1 ma 1.65-2.2v 0.2 v i o l = 1 ma 2.4-3.6v 0.4 v v i h input high voltage 1.65-2.2v 1.4 v d d + 0.2 v 2.4-3.6v 2.0 v d d + 0.3 v v i l (1) input low voltage 1.65-2.2v C0.2 0.4 v 2.4-3.6v C0.2 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a notes: 1. v i l (min.) = C0.3v d c; v i l (min) = -2.0v ac (pulse width < 10ns). not 100% tested. v i h (max.) = v d d + 0.3v d c; v i h (max) = v d d + 2.0v ac (pulse width < 10ns). not 100% tested. absolute maximum ratings (1) symbol parameter value unit v t e r m terminal voltage with respect to gnd C0.2 to v d d +0.3 v t b i a s temperature under bias C40 to +125 c v d d v d d related to gnd C0.2 to +3.8 v t s t g storage temperature C65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rat - ing conditions for extended periods may affect reliability.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll ac test conditions parameter 62wv10248dall 62wv10248dbll (unit) (unit) input pulse level 0.4v to v d d -0.2 0.4v to v d d -0.3v input rise and fall times 5 ns 5ns input and output timing v r e f v r e f and reference level output load see figures 1 and 2 see figures 1 and 2 ac test loads figure 1 figure 2 62w10248dall 62wv10248dbll (1.65v - 2.2v) (2.4v - 3.6v) r1(?) 3070 1029 r2 (?) 3150 1728 v r e f 0.9v 1.5v v t m 1.8v 3.0v r1 5 pf including jig and scope r2 output vtm r1 30 pf including jig and scope r2 output vtm
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll 1.65v-2.2v, power supply characteristics (1) (over operating range) symbol parameter test conditions max. max. unit 55 70 i c c v d d dynamic operating v d d = max., com. 20 20 ma supply current i o u t = 0 ma, f = f m a x ind. 25 25 auto. C 35 typ. (1) 10 i c c 1 operating supply v d d = max., cs1 = 0.2v com. 4 4 ma current we = v d d C 0.2v ind. 4 4 cs2 = v d d C 0.2v, f = 1 m h z a u t o . C 4 i s b 2 cmos standby v d d = max., com. 20 20 a current (cmos inputs) cs1 v d d C 0.2v, ind. 40 40 cs2 0.2v, auto. C 90 v i n v d d C 0.2v, or typ. (1) 4 v i n 0.2v, f = 0 note:. 1. typical values are measured at v d d = 1.8v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll 2.4v-3.6v, power supply characteristics (1) (over operating range) symbol parameter test conditions max. max. unit 45 55 i c c v d d dynamic operating v d d = max., com. 20 17 ma supply current i o u t = 0 ma, f = f m a x ind. 25 22 auto. C 35 typ. (2) 10 i c c 1 operating supply v d d = max., cs1 = 0.2v com. 5 5 ma current we = v d d C 0.2v ind. 5 5 cs2 = v d d C 0.2v, f = 1 m h z a u t o . C 5 i s b 2 cmos standby v d d = max., com. 20 20 a current (cmos inputs) cs1 v d d C 0.2v, ind. 40 40 cs2 0.2v, auto. C 110 v i n v d d C 0.2v, or typ. (2) 4 v i n 0.2v, f = 0 note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll read cycle switching characteristics (1) (over operating range) 45 ns 55 ns 70 ns symbol parameter min. max. min. max. min. max. unit t r c read cycle time 45 55 70 ns t a a address access time 45 55 70 ns t o h a output hold time 10 10 10 ns t a c s 1/ t a c s 2 cs1/cs2 access time 45 55 70 ns t d o e oe access time 20 25 35 ns t h z o e (2) oe to high-z output 15 20 25 ns t l z o e (2) oe to low-z output 5 5 5 ns t h z c s 1/ t h z c s 2 (2) cs1/cs2 to high-z output 0 15 0 20 0 25 ns t l z c s 1/ t l z c s 2 (2) cs1/cs2 to low-z output 10 10 10 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v d d -0.2v/0.4v to v d d -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. ac waveforms read cycle no. 1 (1,2) (address controlled) (cs1 = oe = v i l , cs2 = we = v i h ) data valid previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll ac waveforms read cycle no. 2 (1,3) ( cs1, cs2, oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1= v i l . cs2= we=v i h . 3. address is valid prior to or coincident with cs1 low and cs2 high transition. t rc t oha t aa t doe t lzoe t acs1/ t acs2 t lzcs1/ t lzcs2 t hzoe high-z data valid t hzcs address oe cs1 cs2 dout
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll write cycle switching characteristics (1,2) (over operating range) 45ns 55 ns 70 ns symbol parameter min. max. min. max. min. max. unit t w c write cycle time 45 55 70 ns t s c s 1/ t s c s 2 cs1/cs2 to write end 35 45 60 ns t a w address setup time to write end 35 45 60 ns t h a address hold from write end 0 0 0 ns t s a address setup time 0 0 0 ns t p w e (4) we pulse width 35 40 50 ns t s d data setup to write end 20 25 30 ns t h d data hold from write end 0 0 0 ns t h z w e (3) we low to high-z output 20 20 30 ns t l z w e (3) we high to low-z output 5 5 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v d d -0.2v/0.4v to v d d -0.3v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of cs1 low, cs2 high, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 4. t p w e > t h z w e + t s d when oe is low. ac waveforms write cycle no. 1 ( cs1/cs2 controlled, oe = high or low) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll write cycle no. 2 (we controlled: oe is high during write cycle) write cycle no. 3 (we controlled: oe is low during write cycle) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll data retention waveform (cs1 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd data retention mode data retention switching characteristics (1.65v - 3.6v) symbol parameter test condition min. typ.* max. unit v d r v d d for data retention see data retention waveform 1.4 3.6 v i d r data retention current v d d = 1.4v, cs1 v d d C 0.2v com. 4 20 a ind. 40 auto. 95 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns data retention waveform (cs2 controlled) v dd cs2 0.2v t sdr t rdr v dr ce2 gnd data retention mode * typical values are measured at vdd = 3v, ta = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll is62wv10248dbll (2.4v - 3.6v) industrial range: C40c to +85c speed (ns) order part no. package 55* is62wv10248dbll-55ti tsop-ii is62wv10248dbll-55tli tsop-ii, lead-free is62wv10248dbll-55mi mini bga (9mmx11mm) is62wv10248dbll-55mli mini bga (9mmx11mm), lead-free *when operated in the range for 3.3v 5% or when operated in the temperature range of 0c to 70c, the device meets 45ns. ordering information is62wv10248dall (1.65v - 2.2v) industrial range: C40c to +85c speed (ns) order part no. package 55 is62wv10248dall-55ti tsop-ii is62wv10248dall-55tli tsop-ii, lead-free is62wv10248dall-55mi mini bga (9mmx11mm) is62wv10248dall-55mli mini bga (9mmx11mm), lead-free is65wv10248dbll (2.4v - 3.6v) industrial range: C40c to +125c speed (ns) order part no. package 55 is65wv10248dbll-55ctla3 tsop-ii, lead-free, copper lead-frame
14 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline
integrated silicon solution, inc. www.issi.com 1-800-379-4774 15 rev. a 05/11/09 is 62wv10248dall/bll, is6 5wv10248dall/bll 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/2 /2008

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